【日本專家】PLP for AI/HPC with interposer/substrate materials transitioning from Si/organics to glass | 三建產業資訊

為了創造符合先進AI開發和HPC要求的系統層級性能，需要將多個接近光罩極限大小的先進元件與十幾個HBM進行大規模積體化。由於該封裝的尺寸超過100mm x 100mm，基於現有300mm晶圓製造的CoWoS（晶圓級封裝）開始顯現生產效率和成本效益的極限，因此對PLP（面板級封裝）製程的高品質開發寄予厚望。然而，由於Organic mold基板的翹曲問題尚未充分解決，因此面板級製程進行大規模積體化仍然困難。本課題將整理現有PLP的挑戰，並討論引入Glass interposer和Glass substrate的期望與挑戰。

一、Challenges to ensure PLP process integrity for large size AI/HPC modules
1-1. Warpage issues due to CTE mismatch between EMC and organic interposer materials  
1-2. Advancement in reticle-free direct patterning process on large panel for fine pitch RDL
    
二、Why glass interposers/substrates are emerging

三、Through glass via (TGV) process
3-1. 2-step TGV opening process capability
3-2. Process integration and reliability issues due to thermal stress generated in Cu-filled TGV:
．Protrusion in Cu-filled TGV, glass cracking, Cu peel-offs at sidewall of TGV and at the RDL 
．bottom interface on the glass surface, and their related problems.   
  
四、Future Co-packaged optics integration on glass substrate

五、Closing and Q&A

東芝記憶體、東芝(株)退役專家／專長於半導體封裝設備及材料領域
任職東芝半導體期間，曾歷經Si晶圓、LSI製程開發(先端Device精細化)、Bumping、ChipｰPackage Interaction、半導體設備3D-IC製程開發、Memory事業（TSV、WLP、模組的產品化開發）